1. Field of the Invention
The present invention relates to a delay circuit and, more particularly, to a delay circuit in which delay amounts can be selectively changed for the leading and trailing edges of a pulse waveform.
2. Description of the Prior Art
Recently, as processing speed and the degree of accuracy of logic circuits have become high, the timing accuracy is becoming a significant subject. However, the necessary timing accuracy for a signal is not always obtained as required because of variations in characteristics of component parts, lengths of wiring and floating capacitances of wirings used in the circuit. Due to this, it is necessary to adjust the signal timing so as to match a desired timing by inserting a delay circuit into the signal path for changing the delay amount for every circuit.
FIG. 1 is a block diagram showing one example of a conventional delay circuit, which is a variable delay circuit to attain the above object.
This circuit has a CR integrator consisting of resistors R.sub.A and R.sub.B and variable capacitance diodes D.sub.VCA and D.sub.VCB between buffer amplifiers IC1 and IC2 having the function as comparators, and controls the delay time by varying a value of bias voltage V.sub.B to the variable capacitance diodes D.sub.VCA and D.sub.VCB.
FIG. 2 shows a timechart for the circuit of FIG. 1 and indicates the concept of the delay time control. The propagation delay times in the buffer amplifiers IC1 and IC2 are omitted for easy understanding.
It is now assumed that an input signal as shown in FIG. 2(a) is inputted to an input terminal IN of the buffer amplifier IC1. As shown in FIG. 2(b), the rise time and fall time of the pulse at input terminals A and B of the buffer amplifier IC2 become long under the action of the above-mentioned integrator. By shaping the waveform by the buffer amplifier IC2, the pulse which was delayed by only .DELTA.t as compared with the input signal of FIG. 2(a) is obtained as shown in FIG. 2(c).
In such a conventional circuit, there is a disadvantage such that the delay amounts can not be independently changed for the leading and trailing edges of a pulse waveform.
FIG. 3 shows a prior developed circuit which can independently change the delay amount for leading and trailing edges of a pulse waveform.
A differential amplifier is used and pulses are inputted to the input terminals IN and IN of the buffer circuit (hereinbelow, referred to as the first comparator) 1 having the voltage comparing function such as a comparator, line receiver or the like, and its output terminals are connected to resistors 3 and 4 and a variable capacitance diode 5, and resistors 6 and 7 and a variable capacitance diode 8 as integrators.
The variable reverse bias voltage V.sub.B is applied to the variable capacitance diodes 5 and 8. By varying the voltage V.sub.B, the capacitances of the variable capacitance diodes 5 and 8 are changed and the time constant of the circuit is also changed. Therefore, the leading and trailing times of the waveform at an input 9 on the inverting side of a second comparator 2 similar to the above are changed as indicated by the broken line of FIG. 4(a).
In FIG. 4, the solid lines indicate the waveforms when the capacitances of the variable capacitance diodes 5 and 8 are small, while the broken lines represent the waveforms when those capacitances are large.
On the other hand, in this circuit, the waveform at an input 10 on the non-inverting side of the second comparator 2 is as follows.
Namely, since a diode 11 is connected in parallel to the resistor 3, when an output of the first comparator 1 changes from a Lo level to a Hi level, the diode 11 is made conductive, thereby allowing the variable capacitance diode 5 to be charged within a short time.
On the contrary, when the output of the first comparator 1 changes from a Hi level to a Lo level, the diode 11 is made non-conductive since the reverse bias voltage is applied thereto. Thus, the charged in the variable capacitance diode 5 are gradually discharged by the resistors 3 and 4 and the waveform becomes as shown in FIG. 4(b).
As described above, the waveforms as shown in FIGS. 4(a) and 4(b) are inputted to the second comparator 2. The waveforms as shown in FIG. 4(c) are outputted from the second comparator 2.
In this way, although the delay amount of this circuit is changed by changing the capacitances of the variable capacitance diodes, this is very effective with respect to the trailing edges of the input waveforms.
Namely, the leading and trailing edges can be separated and the delay amounts can be controlled.
FIG. 5 shows the characteristics of this circuit.
Namely, FIG. 5 shows the relations between the bias voltage V.sub.B which is applied to the variable capacitance diodes 5 and 8 and a propagation delay time t.sub.pd in this circuit when emitter coupled logic (ECL) line receivers HD100114 (made by Hitachi, Ltd.) were used as the first and second comparators 1 and 2, and 1SV124 (Hitachi, Ltd.) were used as the variable capacitance diodes 5 and 8, and 1SS165 (Hitachi, Ltd.) was used as the diodes 11.
It will be understood from the graphs that when the bias voltage V.sub.B was changed from 2 V to 14 V, a change amount of the propagation delay time at the trailing edge (hereinbelow, referred to as t.sub.pd .multidot.f) changes from 7.1 nsec to 3.2 nsec as shown by a curve a in FIG. 5.
At this time, a change amount of the propagation delay time at the leading edge (hereinbelow, referred to as t.sub.pd .multidot.r) changes from 3.12 nsec to 2.28 nsec as indicated by a curve b in the diagram.
These characteristic curves are the curves when one desires to actively change the trailing edge. When, for example, an IC is tested, in order to improve the timing accuracy by controlling each edges independently, it is desirable that the timing of the leading edge does not change while the timing of the trailing edge is controlled.
Now, assuming that a degree of separation .eta.=.DELTA.t.sub.pd .multidot.f/.DELTA.t.sub.pd .multidot.r on the basis of a ratio of the change amounts of the delay times between the t.sub.pd .multidot.r at the leading edge and the t.sub.pd .multidot.f at the trailing edge, the characteristics of the circuit are more excellent as a value of this degree of separation .eta. is large.
In the delay circuit of FIG. 3, the degree of separation .eta. is a value of 4.74 as will be obtained from the characteristic curves of FIG. 5.
However, in case of this value, when one desires to change the trailing edge, the leading edge will also have been changed in association with that change. Therefore, when the timings are adjusted with a high degree of accuracy and at a high speed, this value of the degree of separation .eta. is insufficient.
Namely, this delay circuit has an insufficient point such as the lack of degree of separation.
In addition, FIG. 6 shows the output waveform of the delay circuit of FIG. 3. It can be seen from this diagram that the output waveform has ringing due to the influence of the diode 11 connected in parallel to the resistor 3.
Due to this, there is a fear that the circuit of the second comparator 2 on the post side causes a malfunction and when a pulse width is short, there is another fear of occurrence of timing distortion.
Although when the diode 11 is removed, the waveform ringing becomes small, in such a case, there is a disadvantage such that the separation of delay amounts of the leading and trailing edges as mentioned above cannot be obtained.
Further, in this delay circuit, the number of parts is large and the wiring pattern becomes complicated, causing a disadvantage such that the miniaturization is difficult.
As described above, in the conventionally developed delay circuit mentioned above, there are problems such that, fundamentally, a degree of separation is small and the output waveform is distorted and the number of parts is large and the wiring pattern becomes complicated; therefore, it is insufficient although it can be practically used.